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LHF08CTE
24
5.5 V CC , V PP , RP# Transitions
Block erase, byte write and lock-bit configuration are
not guaranteed if V PP falls outside of a valid V PPH1/2/3
range, V CC falls outside of a valid V CC2/3/4 range, or
RP# ≠ V IH or V HH . If V PP error is detected, status
register bit SR.3 is set to "1" along with SR.4 or SR.5,
depending on the attempted operation. If RP#
transitions to V IL during block erase, byte write, or
lock-bit configuration, RY/BY# will remain low until
the reset operation is complete. Then, the operation
will abort and the device will enter deep power-down.
The aborted operation may leave data partially
altered. Therefore, the command sequence must be
repeated after normal operation is restored. Device
power-off or RP# transitions to V IL clear the status
register.
The CUI latches commands issued by system
software and is not altered by V PP or CE# transitions
or WSM actions. Its state is read array mode upon
power-up, after exit from deep power-down or after
V CC transitions below V LKO .
After block erase, byte write, or lock-bit configuration,
even after V PP transitions down to V PPLK , the CUI
must be placed in read array mode via the Read
Array command if subsequent access to the memory
array is desired.
5.6 Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure, byte writing, or lock-bit
configuration during power transitions. Upon
power-up, the device is indifferent as to which power
supply (V PP or V CC ) powers-up first. Internal circuitry
resets the CUI to read array mode at power-up.
A system designer must guard against spurious
writes for V CC voltages above V LKO when V PP is
active. Since both WE# and CE# must be low for a
command write, driving either to V IH will inhibit writes.
The CUI’s two-step command sequence architecture
provides added level of protection against data
alteration.
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled
while RP#=V IL regardless of its control inputs state.
5.7 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is retained
when system power is removed.
In addition, deep power-down mode ensures
extremely low power consumption even when system
power is applied. For example, portable computing
products and other power sensitive applications that
use an array of devices for solid-state storage can
consume negligible power by lowering RP# to V IL
standby or sleep modes. If access is again needed,
the devices can be read following the t PHQV and
t PHWL wake-up cycles required after RP# is first
raised to V IH . See AC Characteristics? Read Only
and Write Operations and Figures 15, 16 and 17 for
more information.
Rev. 1.3
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